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This Role is for a On-site Project Engineer to join a dynamic engineering team. This role involves developing and optimizing Semiconductor Design for a global Semiconductor Design house having a branch in Japan. This role also involves working in a team of overseas engineers to provide technical expertise in Design and Development of a Semiconductor chip to meet strict requirements of Safety principles, Power requirements, Design and manufacturing standards. The candidate is expected to provide innovative solutions to improve functionality and optimize cost in Semiconductor Chip/Chiplets. The role also involves coordination with various stakeholders such as cross-functional teams, manufacturing, testing and validation teams as well as suppliers.

Key Responsibilities

The Onsite Project Engineer role has the main responsibility to lead end-to-end semiconductor design programs across IP/SoC development. The candidate will be a part of the team which handles complex VLSI projects with a strict schedule, scope, and quality targets.

• Hands on Knowledge on Physical aware synthesis

• Develop and Maintain Script flow and scripts

• Good knowledge on Constraints development

• Optimize designs for power, performance, and area (PPA)

• Generate and review reports (timing, area, power, QoR)

• Support low-power implementation (UPF/CPF based flows)

• Hands on knowledge Pre and Post layout Timing analysis for Multi-Mode

• Experience on Logix equivalence check using Industry standard tools like Formality and Conformal

• Knowledge of DFT modes is preferable.

• Hands on Physical design activities like floor planning, power planning, CTS, Routing

Mandatory Skills

• Over 5 years of hands-on experience in semiconductor (SoC) development projects for VLSI/ASIC/SoC domain

• Strong understanding of full chip design lifecycle:

• Architecture → RTL → Verification → Synthesis → P&R → Signoff → Tapeout

• Practical experience in RTL development, verification, or physical design

• Sound Understanding of semiconductor development processes (Lint/CDC/STA/DFT/P&R, etc.)

• Strong knowledge of semiconductor processes (7nm/5nm/advanced nodes preferred)

• Exposure to IP integration or full-chip SoC programs

• Experience of working in day-do-day communication MS-Office tools such MS Word, PowerPoint, Excel, MS teams

• Exposure to collaborating with multi-site / offshore teams

• More than 5 years of project execution experience (schedule, quality, risk management)

• Bilingual Business level Japanese English proficiency (capable of technical discussions via presentations, meetings and email communication)
  

  Soft Skills:

• Ability to organize information and provide clear guidance in technology projects with many uncertainties

• Ability to work in fast-paced, deadline-driven environments

• Strong communication skills to build trust in collaboration with multicultural teams

• Ability to solve problems involving multiple domains through cause analysis and logical approaches

• Excellent stakeholder management & communication skills

• Strong leadership and mentoring ability, Problem-solving and decision-making skills
  

  Desired Experience:

• Experience in advanced nodes (7nm / 5nm / below)

• Exposure to low-power design techniques

• Exposure to UPF

• Experience in high-frequency designs (>1GHz)

• Knowledge of DFT integration

• Experience in SoC-level synthesis
  

  Educational Qualifications:

• Bachelors/master’s degree in Electrical/Electronics/Instrumentation Engineering